Article ID: 000083364 Content Type: Troubleshooting Last Reviewed: 08/21/2013

AN 625: Stratix® V Device Design Guidelines: Known Issues

Environment

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Description

Issue 145244: Version 1.0

Guideline 53 for nIO_PULLUP is not correct.  The option to disable the internal pull-up resistors is not supported on Stratix V devices.  The nIO_PULLUP pin must be connected to GND.

Issue 145253: Version 1.0

Guideline 32 for setting the power-on reset (POR) time is not correct.  It states power sequencing is not a requirement.  This is incorrect - refer to Power Management In Stratix V Devices (PDF) for information on power sequencing requirements. 

Related Products

This article applies to 4 products

Stratix® V GX FPGA
Stratix® V GT FPGA
Stratix® V GS FPGA
Stratix® V E FPGA

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