Article ID: 000083340 Content Type: Error Messages Last Reviewed: 03/25/2013

Critical Warning: Input pin "[pin_name]" feeds inclk port of PLL "[PLL_inst_name]|altpll:altpll_component|pll" by global clock - I/O timing will be affected

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You may see this critical warning in Quartus® II software when you drive a PLL from a clock source that is not the dedicated pin to that PLL. PLLs are designed to compensate for a particular input to output timing relationship depending on the compensation mode selected in your design. When a PLL is fed by a global clock path instead of its dedicated path, the timing relationship on the compensated path is not guaranteed.

This critical warning is triggered by mistake for Quartus II versions 6.1 through 7.2 SP1 for PLLs operating in "no compensation" mode. By definition, a PLL in "no compensation" mode does not have a defined timing relationship between the input clock to output clock destination. This critical warning will be removed in a future version of Quartus II for PLLs operating in "no compensation" or mode.

Resolution

When using a non-dedicated input clock path to the PLL, and if a specific compensation is desired, you should follow these steps to produce the desired TCO (clock to out) timing relationship from the PLL input clock to the output clock destination:

1) Compile your design and perform timing analysis to determine the TCO relationship of your input to output clock path.

2) Adjust the phase of the PLL clock output to compensate for the TCO delay you determined from your timing analysis.

3) Re-compile your design and verify the desired timing for the PLL output clock.

Related Products

This article applies to 7 products

Cyclone® III FPGAs
Stratix® FPGAs
Stratix® GX FPGA
Arria® GX FPGA
Stratix® II GX FPGA
Stratix® II FPGAs
Stratix® III FPGAs

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