Article ID: 000083329 Content Type: Troubleshooting Last Reviewed: 01/07/2019

Why do I see the Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP Design Example packet generator send an extra packet of length >1518?

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Stratix® 10 GX FPGA
  • Intel® Stratix® 10 SX SoC FPGA
  • Intel® Stratix® 10 MX FPGA
  • Intel® Stratix® 10 TX FPGA
  • Intel® Quartus® Prime Pro Edition
  • Low Latency 100G Ethernet Intel® FPGA IP for Arria® 10 and Stratix® V
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    Description

    Due to a bug in the Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP Core Design Example fixed mode and incremental mode, you may see the packet generator send an extra packet of length >1518 in the Ethernet Link Inspector tool TX and RX Statistics section in Statistics Counters Tab (1519 - Max Byte Frames is incremented by 1).

    This problem will not affect the actual 100G Ethernet traffic.

    For example, when the packet range is set between 0x40 to 0x42 with total packets = 10, you could see an extra packet being sent which increments Max Bytes Frames by 1.

    Resolution

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime software.

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