Article ID: 000083328 Content Type: Troubleshooting Last Reviewed: 08/14/2018

Why does Retrain Link with Perform Equalization bit set to 1 cause the Intel® Arria® 10 Gen3 PCIe* Root Port to down train to Gen1 speed?

Environment

  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Intel® Arria® 10 GX FPGA
  • Intel® Arria® 10 GT FPGA
  • Intel® Arria® 10 SX SoC FPGA
  • Intel® Quartus® Prime Pro Edition
  • Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Retraining an Intel® Arria® 10 Gen3 PCIe* Root Port link with Perform Equalization bit (Link Control 3 register 0x304 bit[0]) and Retrain Link bit (Link Control and Status register 0x90 bit[5]) set to 1 may cause the Gen3 link to down train to Gen1 speed. Unlike the Retrain Link bit, the Perform Equalization bit does not get cleared automatically after it is set to 1 , causing the LTSSM to continuously enter the Equalization state and time out.

    Resolution

    To work around this problem, clear the Perform Equalization bit to 0 during the Equalization Phase 3 (ltssmstate: 0x1E) before timeout(24ms) occurs.This problem will not be fixed in a future release of the Intel® Quartus® Prime software.

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