Article ID: 000083325 Content Type: Troubleshooting Last Reviewed: 11/23/2024

Why does the Arria® 10 Multi-Rate Ethernet PHY IP in USXGMII Auto-Negotiation mode fail in simulation?

Environment

    Ethernet 10G MAC Intel® FPGA IP
    Low Latency Ethernet 10G MAC Intel® FPGA IP
    1G 2.5G 5G 10G Multi-rate Ethernet PHY Intel® FPGA IP
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Description

The Arria® 10 Multi-Rate Ethernet PHY IP default value of usxgmii_link_timer at register address 0x412 is 0x7c000. This default reset value sets the link timer to 1.6ms, which is too long in simulation.

Resolution

To work around this problem, set usxgmii_link_timer bit[19:14]=0x01 at address 0x412 to speed up the auto-negotiation process for simulation. This change sets usxgmii_link_timer to the fastest link timer value possible in this register i.e. 0.05ms.

Related Products

This article applies to 1 products

Intel® Arria® 10 FPGAs and SoC FPGAs

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