Article ID: 000083321 Content Type: Troubleshooting Last Reviewed: 02/21/2018

Why does the Deinterlacer II IP core drop a line for every other frame in simulation?

Environment

    Intel® Quartus® Prime Pro Edition
    Deinterlacer II (4K HDR passthrough) Intel® FPGA IP
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Description

Due to a problem with Intel® Quartus® Prime software version 16.1, you may encounter the above problem in simulation if the Deinterlacer II IP core is configured with "Bob" deinterlacing algorithm and produce one frame for every F0 field. 

Resolution

To work around this problem configure the Deinterlacer II IP to produce one frame for every F1 field.

This problem has been fixed in Intel Quartus Prime software version 17.1.

Related Products

This article applies to 9 products

Intel® Arria® 10 FPGAs and SoC FPGAs
Intel® Cyclone® 10 FPGAs
Intel® MAX® 10 FPGAs
Arria® II FPGAs
Arria® V FPGAs and SoC FPGAs
Cyclone® IV FPGAs
Cyclone® V FPGAs and SoC FPGAs
Stratix® IV FPGAs
Stratix® V FPGAs

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