JESD204B IP Core Design Example Simulation Hang When Running in VCS/VCSMX Simulator

The JESD204B IP core design example simulation hangs when you run the simulation file using VCS or VCSMX simulator.

This issue affects all versions that support the JESD204B IP core.

You can disables the debug option if the design example simulation hangs.

For VCS simulator, follow these steps:

1. Open the ed_sim/testbench/synopsys/vcs/run_tb_top.sh file and change the following lines:

<original> . TOP_LEVEL_NAME="tb_top" SKIP_ELAB=1 SKIP_SIM=1 USER_DEFINED_ELAB_OPTIONS="-debug_pp"

<edit> . TOP_LEVEL_NAME="tb_top" SKIP_ELAB=1 SKIP_SIM=1 USER_DEFINED_ELAB_OPTIONS=""

<original> ./simv -ucli -l sim.log -do

<edit> ./simv -l sim.log

2. Open the ed_sim/testbench/models/tb_top.sv file and change the following lines:

<original> (0);

<edit> ;

For VCSMX simulator, follow these steps:

1. Open the ed_sim/testbench/synopsys/vcsmx/run_tb_top.sh file and change the following lines:

<original> vcs -lca -t ps -debug_pp

<edit> vcs -lca -t ps

<original> ./simv -ucli -l record.log -do

<edit> ./simv -l record.log

2. Open the ed_sim/testbench/models/tb_top.sv file and change the following lines:

<original> (0);

<edit> ;