Article ID: 000083308 Content Type: Troubleshooting Last Reviewed: 02/27/2014

Rule C101: Gated clock should be implemented according to the Altera standard scheme

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You may see the following warning when running the Design Assistant tool in Quartus II software on your compiled HPS design. 

Rule C101: Gated clock should be implemented according to the Altera standard scheme ; <hierarchy>:altdq_dqs2_inst|dqsbusout

This warning is expected and can be safely ignored.

Resolution

 

Related Products

This article applies to 6 products

Arria® V GT FPGA
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Arria® V SX SoC FPGA

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