Article ID: 000083299 Content Type: Troubleshooting Last Reviewed: 07/06/2012

Arria V and Arria V GT Designs Fail Hold Time Requirements in TimeQuest Timing Analyzer

Environment

Quartus Edition

Quartus® II Subscription Edition

Version Found: 12.0

FPGA Intellectual Property

Ethernet

Version Found: 12.0

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Critical Issue

Description

This errata affects the Triple-Speed Ethernet MegaCore function.

Designs that target Arria V and Arria V GT 24-Channel Design with LVDS I/O fail hold time requirements in TimeQuest Timing Analyzer.

This issue affects all design that target Arria V and Arria V GT 24-Channel Design with LVDS I/O.

Resolution

Perform seed sweeping to pass the hold time requirement.This issue will be fixed in a future version of the Triple-Speed Ethernet MegaCore function.

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