Floating Point DSP Simulation syntax error, unxpected ';'

Due to a problem in the Intel® Quartus® Prime Software version 15.1 and earlier, you might see one of the following simulation errors when simulating the Floating Point DSP IP component for Intel® Arria® 10 devices.

Mentor:

# ** Error: (vlog-13069) ./../../altera_fpdsp_block_151/sim/<moduleSpecificName>_altera_fpdsp_block_<versionSpecificID> (46): near ";": syntax error, unexpected \';\', expecting \')\'.

Cadence:

ncvlog: *E,EXPRPA (./..//../altera_fpdsp_block_151/sim/<moduleSpecificName>_altera_fpdsp_block_<versionSpecificID>,46|1): expecting a right parenthesis (\')\') [12.1.2][7.1(IEEE)].

Synopsys:

Error-[SE] Syntax error
  Following verilog source has syntax error :
 "./../..//../altera_fpdsp_block_151/sim/<moduleSpecificName>_altera_fpdsp_block_<versionSpecificID>.sv",
  46: token is \';\'
  );

To work around this problem, perform either of the following actions:

1. Generate the VHDL version of the IP and use that in simulations.  
2. Modify the variation file created in / altera_fpdsp_block_151/sim/_altera_fpdsp_block_.sv and change the following line:

    .chainout(chainout

    To:

     .chainout(chainout)

Note: The location of the file can be found in either the 15.0 or 15.1 version so the directory path can be /altera_fpdsp_block_150 or /altera_fpdsp_block_151.

This problem is fixed in the Intel® Quartus® Prime Software v16.0.