Article ID: 000083259 Content Type: Error Messages Last Reviewed: 06/29/2015

Error (10162): Verilog HDL Object Declaration error at <flile>(4616): can't declare implicit net "perstn_pin"

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description You may see this error when compiling a project using the Arria® 10 Avalon®-ST Interface for PCIe® IP.
    Resolution

    Locate the <your Qsys variation>/altera_pcie_a10_hip_150/synth/<your variation>_alterapcie_a10_hip_150_****.v file (where **** is a randomly generated series of characters) and make these changes:

    At line 2026 add this reset synchroniser:
    //=================================
    // Reset synchronizer
    //=================================

    generate begin : g_rst_sync
       if ((interface_type_integer_hwtcl == 1) || (include_sriov_hwtcl == 1)) begin : g_syncrstn_avmm_sriov
             // Reset synchronizer
             altpcie_reset_delay_sync #(
                .ACTIVE_RESET           (0),
                .WIDTH_RST              (10),
                .NODENAME               ("app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl"),
                .LOCK_TIME_CNT_WIDTH    (1)
             ) app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl (
                .clk         (coreclkout_hip),
                .async_rst   (~reset_status),
                .sync_rst(app_rstn[9:0])
             );
       end
    end
    endgenerate

    At line 4378, delete this reset synchroniser
    // Reset synchronizer      
    altpcie_reset_delay_sync #(      
       .ACTIVE_RESET           (0),      
       .WIDTH_RST              (10),      
       .NODENAME               ("app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl"),      
       .LOCK_TIME_CNT_WIDTH    (1)      
    ) app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl (      
       .clk         (coreclkout_hip),      
       .async_rst   (~reset_status),      
       .sync_rst(app_rstn[9:0])      
        );

    At line 4612 change this line:
    .power_on_reset_n           (perstn_pin

    to this:
    .power_on_reset_n           (app_rstn[0]

     

    This problem is scheduled to be fixed in a future release of the Quartus® II software

    Related Products

    This article applies to 3 products

    Intel® Arria® 10 GT FPGA
    Intel® Arria® 10 GX FPGA
    Intel® Arria® 10 SX SoC FPGA

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