LL 40GBASE-KR4 IP Cores with FEC Enabled Fail Simulation

If you turn on FEC in a 40GBASE-KR4 variation of the LL 40GbE IP core, the testbenches fail simulation and the default IP core simulation models fail simulation. This issue occurs because the PCS fails to align and deskew the lanes.

To work around this issue, you must change the value of the SYNOPT_FULL_SKEW RTL parameter in your top-level simulation file to the value of 1. This change increases simulation time.

To change the value of this RTL parameter in the testbench Altera provides with the IP core:

1. Open the <example_design_install_dir>/example_testbench/alt_e40_avalon_kr4_tb.sv file for editing.
2. Change the line

to

This issue will be fixed in a future version of the Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP core.