In the 40GbE and 100GbE MAC and PHY IP Core, the Stratix V RX-Only Configuration Shows Bit Errors on Hardware

In 40GbE and 100GbE MAC and PHY IP Cores with the 12.0 release of the Quartus II software, RX-only configurations for Stratix V device designs such as PHY-only, MAC and PHY, or MAC and PHY with adapters, can show high bit error levels in hardware.

This issue is fixed in the 12.1 Quartus software release of the IP core.

For the 12.0 release of the IP core, reduce the clk_status frequency of the design from 100MHz to 50MHz. This will result in inaccurate clock rate monitor (0x001-0x004) and lock timer (0x011) registers.