Article ID: 000083197 Content Type: Troubleshooting Last Reviewed: 12/18/2018

When using the Intel® Stratix® 10 Avalon -MM Interface for PCI Express* IP Core, how can I read the PCIe* VENDOR ID register at address offset 0x000?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express
  • Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
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    Description

    The address offset given for the PCI* Header Configuration Space Registers in the user guide is only a partial 12 Least Significant Bit (LSB) address offset(4 Kbytes PCIe configuration space). When using the optional Hard IP Reconfiguration block signals the full 21 bit hip_reconfig_address[20:0] must be driven.

     

    Resolution

    This clarification will be added to a future release of the user guide.

    To access Device Identification Registers, such as VENDOR ID etc., the MSB bit of hip_reconfig_address bus must be set to 1'b1.   

    #NOTE: Attempted access of undefined address space have unpredictable results and can cause the PCIe* Hard IP core to stop working, a power cycle is required to recover.

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