Article ID: 000083192 Content Type: Troubleshooting Last Reviewed: 07/22/2016

Is it possible to implement 3 unique clocks inside a single Cyclone, Arria or Stratix device series Logic Array Block (LAB)?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

No, each Cyclone®, Arria® or Stratix® device series LAB can only have up to 2 unique clocks.
Each LAB can however have up to 3 unique clock/clock enable pairs driven by up to 2 distinct clock sources.

Examples of supported configurations are:

CLK_A gated by ENA_A
CLK_B gated by ENA_B
CLK_B gated by ENA_C

OR

CLK_A
CLK_B
CLK_A gated by ENA_A

Example of unsupported configurations are:

CLK_A
CLK_B
not(CLK_A)

OR

CLK_A
CLK_B
CLK_C

Related Products

This article applies to 1 products

Intel® Programmable Devices

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