Article ID: 000083191 Content Type: Troubleshooting Last Reviewed: 09/11/2012

What are the changes required for Basic (PMA Direct) mode configuration in Stratix IV Transceivers if I use Quartus II software version 9.0SP1?

Environment

  • Stratix® IV GX FPGA
  • Stratix® IV GT FPGA
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Altera has identified the following issues in Quartus® II 9.0SP1 for Stratix® IV transceivers Basic (PMA Direct) mode configurations.

1. The tx_clkout frequency in hardware is two times the expected value when the channel width is 16 or 20 bits (Applicable only to PMA Direct xN configuration)

2. Incorrect bit settings in the transceiver-FPGA fabric interface settings in the transmitter and receiver side when the channel width is 16 bits, leading to bit errors.

3. Software Timing models is preliminary which may result in timing violations for designs using Basic (PMA Direct) mode configurations.

To workaround issues 1 and 2, install the patch from the following links for Quartus II Software 9.0SP1 version and recompile the design.

http://www.altera.com/patches/quartus/90sp1/pc_quartus_ii_90sp1_sivgx_patch_1_25.zip
http://www.altera.com/patches/quartus/90sp1/linux_quartus_ii_90sp1_sivgx_patch_1_25.tar
Linux readme.txt -http://www.altera.com/patches/quartus/90sp1/linux_quartus_ii_90sp1_sivgx_patch_1_25.txt

To workaround issue 3, follow the design guidelines and timing constraints provided below

Design Guidelines
a) To meet the setup and hold time requirements on the receiver-FPGA fabric interface, 
Capture receive parallel data (rx_dataout) using the positive edge of recovered clock (rx_clkout) and add the following multi-cycle constraint in the SDC file.
set_multicycle_path -setup -from [get_registers rx_data_reg*] 0
set_multicycle_path -hold -from [get_registers rx_data_reg*] 0
rx_data_reg are the registers used to capture the RX data from the rx_dataout port of the RX PMA in the FPGA core.

If your compiled design using this procedure shows timing violations (depends on transceiver data rate and logic utilization),  use the negative edge of rx_clkout to clock the receive parallel data and remove the above mentioned multi-cycle constraints from the SDC file.

b) To meet the setup and hold time requirements on the FPGA fabric-transmitter interface,
refer to the app note
AN580 -Achieving timing closure in Basic (PMA Direct) modes


Timing Constraints:  Add these constraints in the SDC file only if 9.0SP1 is used. Remove these constraints if you upgrade to Quartus II 9.0SP2 version.

set pma_direct_variation <pma_direct_altgx_module_name>
foreach_in_collection rxpma_clockout_pin [get_pins -compatibility_mode

*|_alt4gxb_*|receive_pma*|clockout]
{
      set rxpma_clockout [get_pin_info -name ]
      regsub "(.*|_alt4gxb_.*|receive_pma\d |)(clockout)" "\1deserclock[0]" rxpma_clocksrc

create_generated_clock -source -master_clock -name


      set_clock_uncertainty -hold -from -to 1.0
}

Replace <pma_direct_altgx_module_name> with the name of the PMA Direct ALTGX module

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