When you run a full timing analysis on a Stratix V design that contains a GXB transceiver block and a Transceiver Reconfiguration Controller megafunction, the TimeQuest timing analyzer reports an unconstraint clock. The timing report shows the following:
alt_xcvr_arbiter:pif.pif_arb|grant was determined
to be a clk but was found wt/o an associated clock assignment
This issue affects Stratix V designs that contain GXB transceiver block and Transceiver Reconfiguration Controller megafunction.
No workaround.This issue will be fixed in a future version of the Triple-Speed Ethernet MegaCore function.