Article ID: 000083172 Content Type: Troubleshooting Last Reviewed: 10/22/2013

Why do the CSR registers report ECC data errors when the read data is not corrupted?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The configuration and status registers (CSR) may report bit errors even though the traffic generator monitor does not detect data corruption when you enable both error correction code (ECC) and CSR in the DDR3 hard memory controller (HMC) MegaWizard™ GUI settings. This discrepancy is seen because the memory controller reads data from uninitialized locations.

Resolution

The workaround of this issue is to load the memory with known content when you enable the ECC feature.

Related Products

This article applies to 14 products

Cyclone® V E FPGA
Cyclone® V SE SoC FPGA
Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Cyclone® V GX FPGA
Arria® V GZ FPGA
Arria® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Arria® V ST SoC FPGA
Arria® V GX FPGA
Arria® V FPGAs and SoC FPGAs
Arria® V GT FPGA
Arria® II GZ FPGA
Cyclone® V FPGAs and SoC FPGAs

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.