Article ID: 000083143 Content Type: Troubleshooting Last Reviewed: 08/24/2012

Cyclone IV GX Timing Model is Missing an MEAB_SEC_LEFT_INPUT Delay

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    In the Quartus II software versions 10.0 SP1 to 12.0 SP1, Cyclone IV GX timing models contain an error that causes zero delay in one input of the secondary input mux to M9K memory blocks. The correct delay is approximately 100 ps to 200 ps (the delay varies by operating condition).The delay is important for designs that contain an MEAB_SEC_LEFT_INPUT element on a path with low slack (that is, a path with slack less than 200 ps), because the erroneous zero delay in the timing model might cause hardware errors.To determine whether this problem affects a particular path, follow these steps:

    1. For the path, in the TimeQuest Timing Analyzer, run Report Timing with the Show routing option turned on.
    2. Inspect the timing report. The zero delay problem affects the path if the element MEAB_SEC_LEFT_INPUT is present on the routing path.
    Resolution

    This problem is corrected in the Quartus II software version 12.0 SP2.

    To properly account for this delay, upgrade to the Quartus II software version 12.0 SP2 and then re-run timing analysis.

    The new timing analysis can reduce the slack on affected paths and as a result might introduce new timing failures. If timing analysis in the Quartus II software version 12.0 SP2 introduces new timing failures, obtain a new fit by re-running Analysis and Synthesis, and Place and Route. The new fit will account for the extra delay on the secondary input mux.

    Related Products

    This article applies to 1 products

    Cyclone® IV FPGAs

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