Article ID: 000083131 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why does my DDR2 SDRAM DIMM design does not work on Stratix III FPGA development kit?

Environment

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Description

If you generate a DDR2 SDRAM High Performance Memory Controller from MegaWizard to interface the DIMM on Stratix® III development kit, you will notice that you will fail calibration stage and will not be able to enter user mode. 

When you generate the DDR2 SDRAM controller, the SDC file (<instance_name>_phy_ddr_timing.sdc) that gets generated has default value of 0.00 for parameter t(additional_addresscmd_tpd) which is the parameter for address/command to clock skew on the board.

set t(additional_addresscmd_tpd) 0.000

For Stratix III FPGA development board, this value is 0.750, therefore you will have to change the value from 0.00 to 0.750 in the SDC file.

set t(additional_addresscmd_tpd) 0.750

Update the SDC file and recompile Quartus® II software project, DDR2 SDRAM DIMM will now pass the calibration stage and the interface will work correctly.

Related Products

This article applies to 1 products

Stratix® III FPGAs

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