How can I find an explanation for the SYNOPT_FULL_SKEW, RST_CNTR, and CREATE_TX_SKEW parameters in the Low Latency 40- and 100-Gbps Ethernet Intel® FPGA IP core simulation testbench?

The following simulation parameters in the Low Latency 40- and 100-Gbps Ethernet MAC and PHY Intel® FPGA IP testbench file are not explained in the user guide.  Refer to the following definitions:

SYNOPT_FULL_SKEW - Support full skew tolerance according to IEEE spec. In the testbench example, this is turned off to speed up the initialization time.

RST_CNTR - controls the reset delays for the PMA reset process. It is set to 6 in simulation to speed up initialization. Ignore this parameter for synthesis and keep the default value.

CREATE_TX_SKEW - Lane-to-lane skew in simulation.

It is important that you do not modify these parameters, otherwise simulation could fail. These parameters are subject to removal in future Quartus® II software releases.

These definitions are not scheduled to be added to the documentation.