Article ID: 000083123 Content Type: Error Messages Last Reviewed: 06/05/2014

Warning (10230): Verilog HDL assignment warning at *instance_name*_write_datapath.v(118): truncated value with size to match size of target (1)

Environment

    Quartus® II Subscription Edition
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You may experience the above warning when compiling the DDR2 or DDR3 SDRAM Controller with UniPHY IP in Quartus II. 

This warning occurs as Quartus II synthesized away some of registers and logics that connected to the 'phy_ddio_oct_ena_pre_shift' signal due to undeclared bus for this signal in <instance name and hierarchy>_write_datapath.v file.  This lead to incorrect OCT switching behavior.

 

Resolution

Declare the \'phy_ddio_oct_ena_pre_shift\' signal as below in the generated <instance name>_write_datapath.v file before their assignment.

wire [AFI_DQS_WIDTH-1:0] phy_ddio_oct_ena_pre_shift;

Related Products

This article applies to 9 products

Stratix® V E FPGA
Stratix® IV GX FPGA
Stratix® V GS FPGA
Stratix® V GT FPGA
Stratix® V GX FPGA
Stratix® IV E FPGA
Stratix® III FPGAs
Arria® II GZ FPGA
Stratix® IV GT FPGA

1

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.