Error: "Index Value (-1) is out of bounds for VHDL object name". (MAX PLUS® II VHDL)

This error may occur in a RANGE FOR LOOP statement, if the 0 bit of a std_logic_vector is assigned explicitly as opposed to using the LOOP variable.

The solution is to make the assignment to bit 0 outside of the LOOP statement and thus modify the RANGE statement in the loop to exclude bit 0.

An example of the code that causes the error is shown below:

SIGNAL cfg_a:        std_logic_vector(32 downto 0);
SIGNAL cfg_edge1:    std_logic_vector(32 downto 0);

cfg_a_proc:   PROCESS(cfgclk)
   BEGIN
      IF (cfgclk 'EVENT and cfgclk = '1') THEN
         FOR i in cfg_a 'RANGE LOOP
            IF (i = 0) THEN
               cfg_a(0) 

A working example is shown below:

SIGNAL cfg_a:        std_logic_vector(32 downto 0);
SIGNAL cfg_edge1:    std_logic_vector(32 downto 0);

cfg_a_proc:   PROCESS(cfgclk)
   BEGIN
      IF (cfgclk 'EVENT and cfgclk = '1') THEN
cfg_a(0)