Article ID: 000083089 Content Type: Troubleshooting Last Reviewed: 05/29/2018

Why does 25G Ethernet IP's dynamic generated example design fail timing in Stratix 10 ES1 and ES2 devices?

Environment

  • Intel® Quartus® Prime Pro Edition
  • 25G Ethernet Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem in Intel® Quartus® Prime Pro version 18.0, the 25G Ethernet IP's dynamic generated example design may fail timing closure.

    The affected variants are as below:

    • 25G with IEEE 1588 Example Design
    • 10G/25G with IEEE 1588 Example Design
    • 25G with IEEE 1588 Example Design and RSFEC
    • 10G/25G with IEEE 1588 Example Design and RSFEC
    Resolution

    Launch Design Space Explorer II and perform seed sweep to get best quality of fitter placement as Stratix® 10 FPGA timing model is still at preliminary stage pending engineering characterization.  

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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