Why does 25G Ethernet IP's dynamic generated example design fail timing in Intel® Stratix®10 FPGA ES1 and ES2 devices?

Due to a problem in Intel® Quartus® Prime Pro Edition Software version 18.0, the 25G Ethernet IP's dynamic generated example design may fail timing closure.

The affected variants are as below:

• 25G with IEEE 1588 Example Design
• 10G/25G with IEEE 1588 Example Design
• 25G with IEEE 1588 Example Design and RSFEC
• 10G/25G with IEEE 1588 Example Design and RSFEC

Launch Design Space Explorer II and perform seed sweep to get the best quality of fitter placement as the Intel® Stratix® 10 FPGA timing model is still at the preliminary stage pending engineering characterization.