Article ID: 000083087 Content Type: Troubleshooting Last Reviewed: 08/14/2018

The Intel® Arria® 10 PCIe* Hard IP does not allow a memory write completion TLP to pass a memory read TLP.

Environment

  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Intel® Arria® 10 GX FPGA
  • Intel® Arria® 10 GT FPGA
  • Intel® Arria® 10 SX SoC FPGA
  • Intel® Cyclone® 10 GX FPGA
  • Intel® Quartus® Prime Pro Edition
  • Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express
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    Critical Issue

    Description

    There is a limitation in the Intel® Arria® 10 PCIe* Hard IP which does not have a bypass buffer to store memory read packets. If there is no credit to send any memory read packets, these packets will stay in the queue which which will cause memory write completion TLPs to be blocked. The Intel® Arria® 10 PCIe* Hard IP does not allow any memory write completion TLP to pass a read memory packet because the Intel® Arria® 10 PCIe* Hard IP does not have a bypass buffer to put memory read packets aside and give way to write completion TLPs.

    Resolution

    No workaround for this problem exists. The user application and software should be aware of the limitation and ensure that this scenario doesn't happen.This problem will not be fixed in a future release of the Intel® Quartus® Prime software.

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