The following critical warnings may occur when a SystemVerilog or VHDL generate statement is used for creating the DDR3 or DDR4 instances in a design:
Critical Warning: The auto-constraining script was not able to detect any PLLs in the <instname> memory interface.
Critical Warning: Verify the following:
Critical Warning: The core <instname> is instantiated within another component (wrapper)
Critical Warning: The core is not the top-level of the project
Critical Warning: The memory interface pins are exported to the top-level of the project
The problematic line in the pin_map.tcl file is in the get_p2c_c2p_clock_uncertainty procedure:
set pll_atoms [get_atom_nodes -matching *${instname}|*:arch|*:arch_inst|*:pll_inst|* -type IOPLL]
Open the pin_map.tcl file, replace *${instname} with *, and re-compile. The design should compile without the critical warnings.
This issue will be fixed in a future version of the Quartus® II software.