The Altera® Avalon®-MM Hard IP for PCI Express® generated using Quartus® II version 14.0 and earlier shows lower throughput when Configuration via Protocol (CvP) is enabled. The problem occurs because the credit counters in the PCIe Hard IP and the Avalon-MM bridge are not synchronized.
For CvP, the PCIe periphery is loaded before the fabric is programmed. After the periphery is programmed, the FPGA transmits and receives PCIe packets. This interaction increments the credit counter in the PCIe Hard IP. Shortly thereafter, the fabric is loaded with the default credit counter values, causing a mismatch between the two counters.
This problem is scheduled to be fixed in a future release of the Quartus® II software.
To work around this problem in Quartus® II version 14.0 and earlier, make the following change in RTL.
In file altpciexpav_stif_tx_cntrl.v, change the following line from:
np_header_avail_reg <= np_header_avail;
To:
np_header_avail_reg <= 1’b1;