Article ID: 000083015 Content Type: Troubleshooting Last Reviewed: 04/23/2013

Does the rx_freqlocked signal assert in simulation if a constant ‘0’ or ‘1’ is applied to the rx_datain signal of Altera transceiver devices?

Environment

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    Description

    Yes the rx_freqlocked signal will assert in simulation if a constant ‘0’ or ‘1’ is applied to the rx_datain signal of Altera® transceiver devices.

    In hardware, the rx_freqlocked signal is not asserted unless the clock recovered from the rx_datain port is within the parts per million (PPM) threshold relative to refclk, as defined in the device handbook.

    To fix the problem, apply ‘Z’ to the rx_datain port in simulation which produces similar behaviour to silicon.

    Related Products

    This article applies to 6 products

    Stratix® II GX FPGA
    Stratix® IV GX FPGA
    Arria® II GZ FPGA
    Stratix® IV GT FPGA
    Arria® II GX FPGA
    Arria® GX FPGA

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