Description
In the Quartus® II software, the Design Assistant may generate different C104 warnings for an FPGA design and its corresponding HardCopy revision because of a limitation in Design Assistant. By default, the Design Assistant only reports warning for 10 nodes.
Resolution
To avoid this limitation, set the following global assignment in your Quartus II Settings File (.qsf):
set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 5000