Article ID: 000083010 Content Type: Troubleshooting Last Reviewed: 06/19/2012

VHDL Post-Fit Simulation Failure on Stratix V Devices

Environment

  • Quartus® II Subscription Edition
  • Simulation
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    This problem affects DDR2, DDR3, QDR II, and RLDRAM II products.

    Error messages similar to the following may occur when running post-fit simulation of VHDL designs:

    # ** Error: /<project_path>/example_project/simulation/modelsim/myDDR3_example.vho(32614): (vcom-1136) Unknown identifier "test_mode". # ** Error: /<project_path>/example_project/simulation/modelsim/myDDR3_example.vho(32615): (vcom-1136) Unknown identifier "use_duty_cycle_correction". # ** Error: /<project_path>/example_project/simulation/modelsim/myDDR3_example.vho(71612): (vcom-1035) Formal port "clkin" has OPEN or no actual associated with it. # ** Error: /<project_path>/example_project/simulation/modelsim/myDDR3_example.vho(183112): (vcom-1136) Unknown identifier "test_mode". # ** Error: /<project_path>/example_project/simulation/modelsim/myDDR3_example.vho(183113): (vcom-1136) Unknown identifier "use_duty_cycle_correction". # ** Error: /<project_path>/example_project/simulation/modelsim/myDDR3_example.vho(225095): (vcom-1136) Unknown identifier "test_mode". # ** Error: /<project_path>/example_project/simulation/modelsim/myDDR3_example.vho(225096): (vcom-1136) Unknown identifier "use_duty_cycle_correction". # ** Error: /<project_path>/example_project/simulation/modelsim/myDDR3_example.vho(237040): VHDL Compiler exiting.

    Resolution

    The workaround for this issue is to modify the post-fit netlist, as follows:

    1. Open the post-fit netlist file <core_name>.vho in a text editor.
    2. Locate and remove the following parameter declaration for stratixv_leveling_delay_chain:
    test_mode => "false" use_duty_cycle_correction => "false"�
    • Ground the clkin port of stratixv_pll_dll_output:
    clkin => "0000"
    • Ground the tdoutap port of stratixv_jtag:
    tdoutap -> ‘0’

    This issue will be fixed in a future version.

    Related Products

    This article applies to 1 products

    Stratix® V FPGAs

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