Article ID: 000083008 Content Type: Troubleshooting Last Reviewed: 05/06/2015

Why is the PCIe Hard IP core not sending out the required flow control (FC) update within 30 us

Environment

  • PCI Express
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description
    Due to an issue with the Altera® PCI Express® Hard IP, FC update may not happen within the required 30us.
    This is due to simultaneous FC Updates for different types of transactions being scheduled.
    This issue causes no system or performance impact.
    For additional information, please contact mySupport with reference FB148571.
    Resolution

     

    Related Products

    This article applies to 5 products

    Stratix® V GX FPGA
    Stratix® V GT FPGA
    Stratix® V GS FPGA
    Stratix® V E FPGA
    Arria® V GZ FPGA

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