Article ID: 000083002 Content Type: Troubleshooting Last Reviewed: 06/28/2016

Does the reset input of the Arria 10 EMIF IP need to be synchronous to the EMIF clock domains?

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BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description No, the global_reset_n input signal is synchronized to the various internal clock domains of the Arria® 10 EMIF IP before being used.

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