Critical Issue
Description
If you create an Arria V Transceiver Native PHY IP core megafunction
in the MegaWizard Plug-In Manager and you enable the Use external
TX PLL option to expose the ext_pll_clk port to an external
transmitter (TX) phase-locked loop (PLL), both ext_pll_clk and tx_pll_refclk ports
appear in the block diagram but only the ext_pll_clk port is used
in the IP core.
Resolution
There is no workaround.