Article ID: 000082996 Content Type: Troubleshooting Last Reviewed: 07/19/2015

spl.c:427:4: error: 'rst_mgr_status' undeclared (first use in this function)

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description This error may be seen when compiling a Software Preloader (SPL) for Cyclone® V SOC or Arria® V SOC  in the SoC EDS software version 15.0.1,  if  WARMRST_SKIP_CFGIO is disabled.
    Resolution

    To work around this problem in SoC EDS 15.0.1 either enable WARMRST_SKIP_CFGIO, or follow the steps below:

    1. Enable “CONFIG_HPS_RESET_WARMRST_HANDSHAKE_SDRAM” for your SPL BSP in the advanced section of the  BSP-Editor GUI
    2. Re-generate the BSP
    3. Re-compile the SPL: Run make clean and make in your generated SPL directory

    This problem is scheduled to be fixed in a future version of the SoC EDS software.

    Related Products

    This article applies to 5 products

    Arria® V ST SoC FPGA
    Arria® V SX SoC FPGA
    Cyclone® V SE SoC FPGA
    Cyclone® V ST SoC FPGA
    Cyclone® V SX SoC FPGA

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