The Altera® engineering team performs many tests on the Stratix® GX and Stratix II GX functional simulation models in every HSSI configuration supported by the Quartus® II software. Functional RTL simulation and functional post-layout netlist simulation is performed with different simulators, including Synopsys VCS, Cadence NC-Sim and Mentor Graphics® ModelSim® .
Altera also verifies the gigabit transceiver block (GXB) simulation models by simulating post-layout netlists (.vo and .vho) and timing-annotated Standard Delay Output file (.sdo). Because the GXB High-Speed Serial Interface (HSSI) block is hard IP that is verified in the device silicon, no timing delays are required for simulation of this block. Instead, setup and hold time checks are added in the .SDO file to ensure that your design meets the block's timing requirements.