Critical Issue
Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 18.0 Update 1 and earlier, you may see this synthesis error message during compilation when a 50G Interlaken Intel® FPGA IP is instantiated in an Intel® Arria® 10 design.
To work around this problem, add the following in the Quartus Setting File (.qsf) to prevent the affected register being inferred as altshift_taps.
For example:
set_instance_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -to * -entity ilk_iw4_rx_channel_filter
This problem is fixed starting in the Intel® Quartus® Prime Pro Edition Software version 18.1.