Article ID: 000082957 Content Type: Error Messages Last Reviewed: 04/30/2018

Error (16058): PLLs that use the x1 clock network and drive the same HSSI channel must be placed in the same transceiver bank

Environment

  • SDI II Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem with Intel® Quartus® Prime Standard software version 17.1, you may observe the above error if you are using Intel® FPGA SDI II IP with dynamic TX PLL switching enabled in Intel® Arria® V devices.

    Resolution

    There is no workaround for this problem. This problem will be fixed in a future version of the Quartus Prime Standard software.

    Related Products

    This article applies to 1 products

    Arria® V FPGAs and SoC FPGAs

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