Article ID: 000082955 Content Type: Product Information & Documentation Last Reviewed: 08/30/2018

How do I successfully perform a lane swap such as the one performed for the QSFP interface of the Intel® Stratix® 10 GX FPGA Development Kit when using the Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Core?

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Ethernet
  • Low Latency 40G 100G Ethernet
  • Low Latency 40G Ethernet Intel® FPGA IP for Arria® 10 and Stratix® V
  • Low Latency 100G Ethernet Intel® FPGA IP for Arria® 10 and Stratix® V
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    If you are swapping lanes on your PCB for improved signal routing and using the Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP Core, do not also swap the pin assignments of the Intel Stratix 10 device.

    Instead, leave the original Stratix 10 device pinout and utilize the lane reordering feature supported by the PCS of the Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Core.

    The lane reordering feature supported by the of the Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Core allows the user swap any physical connections as they please without altering the Stratix 10 device pinout.

    The lane reordering occurs automatically in the Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Core and no additional register settings are required. 

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