Article ID: 000082954 Content Type: Troubleshooting Last Reviewed: 02/08/2018

Why does my Intel® Stratix® 10 PCIe* example design fail to enumerate?

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
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    Description

    Due to a problem with the Intel® Quartus® Prime software version 17.1, the dynamic example designs generated from Platform Designer or IP Catalog are missing some pin location assignments. As a result these designs can fail enumeration, possibly resulting in the LTSSM holding at the Detect state or cycling between the Detect and Polling states.
     

    Resolution

    To work around this issue, assign the test_in signals to virtual pins and assign the npor input to a pin which defaults to a high (true) state. 

    • The test_in assignment will hold all those signals deasserted, which will prevent the PCIe* IP from going into a test mode.
    • Connecting npor to a high input will prevent npor from being asserted and holding the PCIe* IP in reset.  On the Intel® Stratix® 10 GX development kit, you could connect npor to pin B20 which is a user pushbutton with a pullup.

    You can make these assignments in the Assignment Editor, or directly edit the .qsf file to add these lines:

    set_instance_assignment -name VIRTUAL_PIN ON -to hip_ctrl_test_in -entity pcie_example_design

    set_location_assignment PIN_B20 -to pcie_rstn_npor

    This problem is scheduled to be fixed in a future Intel® Quartus® Prime software release.

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