Article ID: 000082948 Content Type: Troubleshooting Last Reviewed: 12/04/2024

Why might the RapidIO* IP Core transmit incorrect packets during retries?

Environment

    Intel® Quartus® Prime Pro Edition
    RapidIO (IDLE1 up to 5.0 Gbaud) Intel® FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You may encounter the RapidIO* transmitter sending out corrupt packets.

This problem may be caused by the RapidIO* IP Core transmitter timeout/timestamp counter not being reset correctly during retries.

 

 

Resolution

This problem is scheduled to be fixed in a future version of the Quartus® Prime Software.

Related Products

This article applies to 10 products

Cyclone® V GX FPGA
Stratix® V FPGAs
Cyclone® V SX SoC FPGA
Stratix® IV GT FPGA
Stratix® IV GX FPGA
Intel® Arria® 10 FPGAs and SoC FPGAs
Cyclone® V ST SoC FPGA
Arria® V FPGAs and SoC FPGAs
Arria® II FPGAs
Cyclone® IV GX FPGA

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