Article ID: 000082938 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why does my formal verification report inequivalent results when my design uses a SignalTap II logic analyzer?

Environment

  • Verification
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    If your design uses the SignalTap® II logic analyzer, formal verification reports mismatches. The Quartus® II formal verification flow is not supported with Cadence Conformal LEC if you use the SignalTap II logic analyzer in your design.

    Related Products

    This article applies to 1 products

    Stratix® II FPGAs

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