Article ID: 000082868 Content Type: Error Messages Last Reviewed: 02/13/2006

Error: <<I>filename</I>>: "VHDL syntax error: expected choices in case statement. (MAX PLUS® II)

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description You may see this error when synthesizing a VHDL CASE statement in the MAX PLUS II software if there is no WHEN OTHERS clause in the design.

For example, the following code causes the above error, where input_a and output_b are declared as STD_LOGIC:

CASE input_a IS
     WHEN '0' =>
          output_b 
          output_b 
          output_b 
          output_b

Related Products

This article applies to 1 products

Intel® Programmable Devices

1

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.