Simulation Example Design Fails and Produces Warnings

This problem affects DDR2 and DDR3, LPDDR2, QDR II, and RLDRAM II products.

The simulation example design may stop responding and issue warnings similar to the following:

# 3271428747 Note : Input frequency on DLL instance ddr3_ctrl_av_example_sim.e0.if0.dll0.dll_wys_m.inst now matches with specified clock frequency. # 3271457497 Warning : Input frequency violation on DLL instance ddr3_ctrl_av_example_sim.e0.if0.dll0.dll_wys_m.inst. Specified input period is 2500 ps but actual is 3750 ps

The workaround for this issue is as follows:

1. In a text editor, open the simulation example design top-level file (for example, corename_example_sim.v).
2. In the simulation example design top-level file, change the reference clock BFM clock rate to match the required frequency in MHz.

For example, for the pll_ref_clk instance of altera_avalon_clock_source, replace.CLOCK_RATE (32)

with

This issue will be fixed in a future version.