Critical Issue
Description
When simulating with VHDL in Cadence® NC-Sim®, the 13.0 Quartus® II software release of the Deterministic Latency PHY IP Core fails because the wrong parameter sequence is set between the Verilog top level and the generated VHDL. Verilog simulations in Cadence NC-Sim are not affected.
Resolution
There is no workaround for the 13.0 Quartus II software release. You must use a newer release to simulate VHDL in Cadence NC-Sim.
This issue is fixed in the 13.1 Quartus II software release.