Article ID: 000082819 Content Type: Troubleshooting Last Reviewed: 01/12/2018

Why does the Intel® DisplayPort IP have no audio transport for small horizontal blanking periods?

Environment

    Intel® Quartus® Prime Pro Edition
    DisplayPort Intel® FPGA IP
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Critical Issue

Description

Due to a problem with the DisplayPort IP, the DisplayPort TX core is not able to transport any audio sample when the resolution of horizontal blanking is smaller than the period shown below.

  • For quad symbol mode (SYMBOLS_PER_CLOCK = 4)
    • The minimum horizontal blanking period (in link clock cycles) to transport audio is 22, 21, 20 for transceiver lanes 1, 2, and 4, respectively. 
  • For dual symbol mode (SYMBOLS_PER_CLOCK = 2)
    • The minimum horizontal blanking period (in link clock cycles) to transport audio is 38, 35, 34 for transceiver lanes 1, 2, and 4, respectively. 
Resolution

This problem is fixed in version 17.0 of the Intel® Quartus® Prime software.

Related Products

This article applies to 4 products

Arria® V FPGAs and SoC FPGAs
Cyclone® V FPGAs and SoC FPGAs
Stratix® V FPGAs
Intel® Arria® 10 FPGAs and SoC FPGAs

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