Article ID: 000082816 Content Type: Troubleshooting Last Reviewed: 02/26/2018

Why does Intel® Stratix® 10 PCIe* Hard IP with SR-IOV drop outstanding completion TLPs of different PFs that use the same tag value?

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem with the Intel® Stratix® 10 PCIe* Hard IP with SR-IOV that improperly tracks tag value across physical functions (PFs), the Hard IP drops subsequent completion TLPs for a different PF that has the same tag value if that particular tag value is being actively tracked for another PF's non-posted request.

    Resolution

    To work around this problem, use unique tag value for outstanding non-posted requests from different PFs.

    This limitation and workaround will be documented in a future version of the Intel® Stratix® 10 Avalon®-ST and Single Root I/O Virtualization (SRIOV) Interface for PCIe* Solutions User Guide.

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