Why don't reset_rx_clk and reset_tx_clk signals of PCS-only variant and PCS plus PMA variant of the Triple Speed Ethernet Intel FPGA IP synchronize to the rx_clk and tx_clk signals?

The reset_rx_clk and reset_tx_clk signals of PCS-only variant and PCS-plus-PMA variant of the Triple Speed Ethernet Intel® FPGA IP are not synchronized to the rx_clk and tx_clk signals.

The following patch provides a solution to ensure that the reset_rx_clk signal is synchronized to the rx_clk signal and the reset_tx_clk signal is synchronized to the tx_clk signal.

Download the following Quartus® II software version 10.1 SP1 patch 1.77:

• Quartus II software version 10.1SP1 patch 1.77 for Windows
• Quartus II software version 10.1SP1 patch 1.77 for Linux
• Quartus II software version 10.1SP1 ReadMe for patch 1.77

Caution:

You must either have installed the Quartus II software v10.1 SP1 previously or install the Quartus II software v10.1 SP1 before installing this patch. Otherwise, the patch will not be installed correctly and the Quartus II software will not run properly.

After you have installed the patch, regenerate your Triple Speed Ethernet Intel FPGA IP before you compile your design.