Due to a problem in Quartus® II software version 13.0, Qsys generation reports the following error when the PCIe® coreclkout drives the input clock of the SPI component.
Info: dac_config_spi: Illegal division by zero at D:/altera/13.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_spi/em_spi_qsys.pm line 338.
Error: dac_config_spi: Failed to generate module avalon_system_dac_config_spi
This error occurs because the PCIe component definition does not correctly declare the “clockRateKnown” of the interface. Thus the SPI component defaults to a clock rate of 0.0Hz.
Open the pcie_av_avmm_parameters.tcl file located at
/../ip/altera/altera_pcie/altera_pcie_av_hip_avmm directory
On line 1418, insert the following text as a new line:
set_interface_property coreclkout clockRateKnown true
Upon refreshing the system the SPI component assumes the correct clock rate and the system will then generate correctly.