Article ID: 000082711 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Can the rx_st_valid signal get deasserted even though rx_st_ready is still asserted?

Environment

  • PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description Yes, the rx_st_valid signal can get deasserted even when rx_st_ready is asserted. This behavior can be more prevalent in 128-bit interfaces when you do multiple Memory Writes (MWr) even though other transactions can lead to this behavior as well.

    Related Products

    This article applies to 2 products

    Stratix® IV GX FPGA
    Stratix® IV GT FPGA

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.