Article ID: 000082676 Content Type: Product Information & Documentation Last Reviewed: 12/05/2018

How do I enable the Loopback Master option of the Intel® Stratix® 10 Hard IP for PCI* Express Root Port?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
  • Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Beginning with Intel® Quartus® Prime Pro v18.0 Update 1 software, you can enable Loopback Master option for the Intel® Stratix® 10 Hard IP for PCI* Express Root Port.

    Resolution

    To enable the Loopback Master option of the Intel® Stratix® 10 Hard IP for PCI* Express Root Port:

    1. Open the IP GUI
    2. Right click on the Intel Stratix 10 Hard IP for PCI Express banner and select Show Hidden Parameters
    3. Scroll down until you see the Enable Loopback Master option and select it
    4. Do not modify any other hidden parameters
    5. Right click on the Intel Stratix 10 Hard IP for PCI Express banner and select Hide Hidden Parameters (optional but recommended)
    6. Select Generate HDL

     

    This Loopback Master function is for link testing only.  For normal PCIe* operation, deselect the Loopback Master option, regenerate HDL, and reimplement the design.

     

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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